1. Field of the Invention
This invention relates to integrated circuits, and particularly to metal oxide semiconductor large scale integrated circuit (MOS LSI) devices having n-channel or p-channel MOS field effect transistors, such as are commonly used in hand calculators, home and office computers, automotive and industrial control systems and other commercial products. MOS LSI devices use numerous circuit designs to achieve specific functions. One of the circuit designs used in MOS LSI devices is a differential comparator circuit, i.e., a circuit which amplifies the voltage difference between a signal input terminal and a reference signal input terminal. The invention ac coupled, chopper stabilized differential comparator circuit is particularly useful in MOS LSI devices operating in synchronous fashion based on a master clock signal. The invention circuit provides high differential voltage gain through one or more stages of amplification with minimum error from amplifier offset voltage.
2. Description of the Prior Art
Differential comparator circuits are known in the art. MOS LSI versions of these circuits are being used in memory sense amplifier applications. They typically have input sensitivities of 100 millivolts or more. In analog-to-digital converters much higher sensitivities are required. The low drift and good gain matching characteristics required of a differential comparator circuit used for such an application are difficult to obtain using present MOS LSI integrated circuit processing steps.
The invention ac coupled, chopper stabilized differential comparator circuit overcomes the above disadvantages and is easily implemented in MOS LSI circuits using insulated gate field effect transistors (IGFETs) and which require clocked or synchronized operation.
Differential comparators typically have an offset voltage that is unpredictable within a predetermined input voltage range. Connecting the output of a first state differential comparator to the input of a second stage differential comparator results in the offset voltage of the first stage differential comparator being amplified by the second stage differential comparator. The amplified offset voltage is an error voltage tending to mask a valid differential input signal. A third stage differential comparator compounds the error contribution. The invention ac coupled, chopper stabilized differential comparator circuit allows multiple stages of amplification to be used while processing only a small portion of the offset voltage of the first stage with the input signal. The invention circuit requires no trimming and is particularly compatible with manufacturing techniques to implementation in MOS processes for implementing n-channel, p-channel, metal gate or silicon gate devices using single or double polysilicon layers or other known techniques.